In a move that could redefine the economics of semiconductor manufacturing, Huawei is challenging the traditional pursuit of smaller fabrication nodes. The company's rotating chairman, Xu Zhijun, recently revealed that cutting-edge chip performance can be achieved using mature 7-nanometer-class process technology by implementing a new design methodology known as "He's Law" or the "Tau Scaling Law" (τ-law).
The methodology, first presented by He Tingbo, president of Huawei's semiconductor business, at the IEEE International Symposium on Circuits and Systems (ISCAS), seeks to decouple high performance from the skyrocketing costs associated with the newest, smallest fabrication nodes. According to Xu, this approach allows chipmakers to produce high-performance chips at a significantly lower cost, posing a compelling alternative to the industry's standard trajectory.
While the tech world has long been guided by Moore's Law—the observation that transistor density doubles roughly every two years—Xu emphasized that He's Law is not intended as a replacement. Instead, it is a practice-tested approach focusing on reducing the time constant (τ) across device, circuit, chip, and system levels, rather than relying exclusively on the physical shrinking of transistors.
The core innovation behind this methodology is a technique called "logic folding." In this process, multiple dies are designed as a single integrated unit from the outset, which allows for superior critical-path optimization. To illustrate the difference between logic folding and conventional 3D stacking, Xu used a simple analogy: "Folding means folding a single sheet of paper; stacking means putting two separate sheets on top of each other."
This shift in strategy is driven largely by economic necessity. As the costs of developing and producing chips at the most advanced nodes become increasingly unsustainable, logic folding on mature nodes offers a more viable financial path for manufacturers.
The industry will see the first commercial application of this technology later this year with the release of the Kirin 2026 chip, the first mobile processor to utilize logic folding. Looking further ahead, Huawei expects this design philosophy to enable transistor density equivalent to 1.4nm-class technology by 2031.
Reference(s):
How will Huawei build cutting-edge chips with cheaper 7nm tech?
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